JOB DESCRIPTION

You will need to bring a solid background in CPU Architecture, including knowledge of cache architectures and cache coherency; memory subsystem design and memory ordering; semaphores and threading. Combine that with your object oriented software skills and by working with our senior engineers, we will bring you up the curve on the latest techniques in themeprocessor verification. Prior experience doing simulation based verification of small to medium complexity blocks is highly desirable. Included in this work is writing various testbench components (stimulus generators, checkers, coverage objects, directed/random tests, etc) and resolving/debugging failures accordingly. You will need a desire to learn, and be a motivated self starter who enjoys challenges and is good at debugging and solving problems.

MARGINAL FUNCTIONS:
* Verilog coding of simple logic functions
* HTML/web page editing

REQUIRED KNOWLEDGE:
* Junior/Senior student
* Bachelor or Masters candidate in EE, CE or CS
* Course work in VLSI design and design verification
* Experience with a Hardware Description Language (HDL) such as Verilog
* Strong understanding of computer architecture
* Independent / self-starter
* Strong debugging skills
* GPA 3. 5 or higher

PREFERRED KNOWLEDGE:
* Experience with ASIC or design verification methodologies
* An understanding of test coverage and random test generation
* Knowledge of testbench languages such as vera or specman highly desireable.
* Strong documentation and writing skills

YEARS OF EXPERIENCE:
0-1

MINIMUM LEVEL OF EDUCATION:
BS

FIELD OF STUDY:
EE, CE, or CS

ADDITIONAL COURSE WORK:
Design Verification Engineering

k@mille System is an equal opportunity employer and appreciates your desire to be considered for a position. k@mille only accepts resumes submitted through the Internet: